Solder bump connections have been used for mounting IC's (integrated computer chips) using the C4 (controlled collapse chip connection) technology since first suggested in U.S. Pat. Nos. 3,401,126 and 3,429,040 by Miller. In Packaging Electronic Systems by Dally (McGraw-Hill 1990 p. 113) "Chip bond pads are deployed in an area array over the surface of the chip. . . . These bonding pads are 5 mil in diameter on 10 mil centers. Matching bonding pads are produced on a ceramic substrate so that the pads on the chip and the ceramic coincide. Spheres of solder 5 mil in diameter are placed on the ceramic substrate pads . . . and the chip is positioned and aligned relative to the substrate. The assembly is heated until the solder spheres begin to soften and a controlled collapse of the sphere takes place as the solder simultaneously wets both pads. A myriad of solder structures have been proposed for mounting IC chips as well as for interconnection to other levels of circuitry and electronic packaging."
Reflow transfer of solder from decals has been developed for depositing eutectic solder for attaching flip chips to metal pads on organic substrates. Stainless steel decals are coated with a thin layer of photoresist which is photo-developed to provide windows in the same pattern as C4 connectors on a flip chip. A thick layer of eutectic Pb/Sn solder is electroplated onto the decals at the windows. The decal is positioned on an organic carrier aligned with connection pads and heated to reflow transfer the solder from the decal onto the pads on the carrier. Then a flip chip is placed on the carrier with C4 pads on the solder and reflow heated to connect the chip to the pads.
Use of epoxy encapsulants to enhance fatigue life of flip-chip connection is suggested in U.S. Pat. Nos. 4,999,699; 5,089,440, and 5,194,930 all to Christie. U.S. Pat. No. 4,604,644 to Beckham suggests materials and structures for encapsulating C4 connections. U.S. Pat. No. 4,701,482 to Itoh and U.S. Pat. No. 4,999,699 of Christie et al. disclose epoxies and provide guidance in selecting epoxies for electronic applications.
"Ball grid arrays: the hot new package" by Terry Costlow and "Solder balls make connections" by Glenda Derman both in Electronic Engineering Times Mar. 15, 1993, suggest using solder balls to connect ceramic or flexible chip carriers to circuit-boards. Ball grid array modules include components with plastic (organic), ceramic, and tape carrier substrates known as PBGA, CBGA, and TBGA molues respectively.
Fabrication of multi-layer ceramic chip carriers is suggested in U.S. Pat. Nos. 3,518,756; 3,988,405; and 4,202,007 as well as "A Fabrication Technique For Multi-Layer Ceramic Modules" by H. D. Kaiser et al., Solid State Technology, May 1972, pp. 35-40 and "The Third Dimension in Thick-Films Multilayer Technology" by W. L. Clough, Microelectronics, Vol. 13, No. 9 (1970), pp. 23-30. Common ceramic materials for electronic packaging substrates include alumina, beryllia, and aluminum nitride. "Pinless Module Connector" by Stephans in IBM Technical Disclosure Bulletin Vol. 20, No. 10, March 1978, suggests a ceramic ball grid array module with copper balls. U.S. Pat. No. 5,118,027 to Braun suggests placing solder balls in an alignment boat, vacuum holding the balls while eutectic solder is deposited on the balls, aligning the boat with conductive pads on a substrate, reflowing in an oven and then removing the boat. EP 0,263,222 A1 to Bitaillou suggest attaching solder balls to vias in a ceramic substrate to form a ball grid array module.
U.S. Pat. No. 4,914,814 to Behun, suggests casting columns onto pads to form ceramic column grid array modules, a graphite plate is drilled with through-holes corresponding to metal pads on the bottom of a chip carrier substrate, then preforms of 3/97 Sn/Pb solder are placed in the holes. Then the plate and carrier substrate are heated to melt the preforms to connect liquid solder to the pads, then the plate and carrier substrate are cooled and the plate is moved away from the carrier leaving the columns cast to the pads.
U.S. Pat. No. 4,752,027 to Gschwend suggests methods of bumping printed circuit boards for attaching modules, including screening solder paste, reflowing the paste to form bumps, and using rollers to flatten the solder bumps. U.S. Pat. No. 4,558,812 to Bailey suggests using a vacuum plate to simultaneously deposit an array of solder balls on a substrate.
Fabrication of multi-layer rigid organic circuit-boards is suggested in U.S. Pat. Nos. 3,554,877; 3,791,858; and 3,554,877. Thin film Techniques are suggested in U.S. Pat. No. 3,791,858.
Flexible film chip carriers (known in the art as Area Tape Automated Bonding (ATAB) modules or TBGA modules) are suggested in U.S. Pat. Nos. 4,681,654 and 5,159,535 and 4,766,670. In ATAB a flexible circuit-board chip carrier is mounted on a circuit-board using solder ball connect. U.S. Pat. Nos. 5,057,969 to Ameen, and 5,133,495, 5,203,075, and 5,261,155 to Angulas suggests using solder balls to connect TBGA modules to circuit boards.
U.S. Pat. No. 5,261,593 to Casson suggests providing solder paste on a plurality of contact pads on a flexible printed circuit substrate (polyimide); placing flip-chips on the substrate with solder bumps of the flip-chip in registration with the pads; and heating to reflow the paste to electrically connect the bumps to the pads. According to Casson bumped flip-chips are un-packaged meaning they have no plastic shells nor metallic leads. Casson describes bumping chips (C4) by sputtering titanium/tungsten to promote adhesion to a passivation layer; sputtering copper; applying and developing a photoresist; electroplating copper and then 3/97 to 10/90 Sn/Pb or 63/35/2 Pb/Sn/Ag solder; removing the photoresist; and wet etching the exposed copper and titanium/tungsten to form 9 mil diameter bumps about 4.5 mil high (60 mils.sup.3). He also suggests producing flexible Novaclad.RTM. (polyimide film with sputtered copper by E. I Du Pont de Nuemers) circuit substrates; optical alignment of stencils with substrates; screening 63/37 Sn/Pb solder paste through a 4 mil stencil with 14 mil openings with a round squeegee of 90 durometer at 1.5 inches/second and 22 psi pressure to provide 6E-7 in.sup.3 deposits on pads of flexible substrates; self alignment during reflow heating using vapor phase or in IR or convection ovens; and epoxy chip encapsulation.
U.S. Pat. No. 3,781,596 suggests a single layer interconnection structure of metallic conductors on a polyimide film (e.g. KAPTON.TM. by E. I. DuPont de Numers). U.S. Pat. No. 3,868,724 suggests metallic conductors sandwiched between polyimide film, which projects through the film. U.S. Pat. No. 5,112,462 to Swisher suggests producing adhesivless flexible substrates of polyimide film and copper sputtered and then electroplated onto the film.
Floropolymer based films have been proposed for flexible circuit-boards such as PTFE filled with ceramic, or glass particles or fibers such as woven fiberglass, and Kevlar.RTM. (by Chemfab Corporation). Gore Company makes woven PTFE fabrics for impregnating with resins to form flexible dielectric substrates. Also molded thermoplastics have been used for flexible one sided and double sided circuit-boards.
Connecting components directly to one side of a single-layer flexible circuit-board is described by McBride in "Multi-function Plug for IC Package", IBM Technical Disclosure Bulletin, Vol, 21, February 1979, pp. 3594-3595. I/O terminals on the bottom of a chip are soldered to pads on top of a thin polyimide flexible decal. Also, a depression in a heat sink cover is bonded onto the top of the chip. Connecting lower power chips to a bottom side of a multi-layer flexible circuit-board and high power chips to the top side of the flexible circuit-board in order to connect the high power chips to the module cap is suggested by McBride, "Multilayer Flexible Film Module", IBM Technical Disclosure Bulletin Vol 26, May 1984, p 6637. In that article I/O pins connect the flexible film to a metalized ceramic substrate, and smaller pins interconnect the layers of the film. Schrottke, "Removal of Heat from Direct Chip Attach Circuitry" IBM Technical Disclosure Bulletin Vol 32, September 1989, pp. 346-348 describes a flexible circuit-board with two rows of Direct Chip Attach (DCA) chips attached by controlled collapse chip connections (C4). The flexible circuit-board is folded around a stiff heat spreader of copper-INVAR-copper (INVAR is a trademark of Creusot-Loire for nickel-iron alloys) the coefficient of thermal expansion (CTE) of INVAR can be controlled by varying the ratio of nickel and iron and by varying the thickness of plated metal coatings such as copper.
U.S. Pat. No. 4,967,950 to Legg suggests tinning contact pads with eutectic solder metal and positioning a flip-chip with C4 bumps on the solder on the pads.
U.S. Pat. No. 5,147,084 to Behun, suggests using a HMP (high melting point) solder ball in association with a LMP (low melting point) solder. "A part 10 is to be joined to a board 11. Part 10 has internal metallurgy 14 which terminates at the surface at a bonding pads 12. A . . . LMP solder 16 is applied to a bonding pad 12. A . . . HMP solder ball 18 is placed in contact with LMP solder 16 and the assembly is heated to reflow the LMP solder which then wets to the non-molten HMP solder ball. . . . Board 11 is also illustrated with internal metallurgy 15, terminating on the surface bonding pad 17. . . . the assembled part 10 . . . is brought into contact with part 11 having pad 17 and LMP solder 13, and the two are heated to a temperature sufficient to reflow the LMP solder but not sufficient to melt the HMP solder ball. The LMP solder 13 which is attached to the bonding pad 17, on board 11, will wet the HMP ball and connection will be achieved."
Solders have a melting temperature range extending from a solidus temperature to a liquidious temperature in which range they have a pasty consistency that varies with temperature from solid to liquid respectively over the range. Molten refers to heating sufficiently to wet to another material or cure to another material in the case of epoxies and thermoplastics containing solvents.
U.S. Pat. No. 4,825,034 to Auvert suggests a micro-beam laser machine for acting on thin layers of materials especially integrated circuits. Laser cutting and welding machines for making stencils are available from Messerchmitt Bolkow Blohm, Northern Plant, 7312 Kirchheim/Teck Nobern.
"Ball Grid Array Module Solder Stencil Template" by Isaacs et al. in IBM Technical Disclosure Bulletin vol. 37, No. 06B, June 1994, p. 225, suggests a template or spacer to supporting a stencil to screen solder paste onto distal ends of ball grid array balls and column grid array columns for rework.
"Solder Preform Technique for Fine Pitch Surface Mount Technology components" by Nilsen et al. in IBM Technical Disclosure Bulletin, Vol. 36, No. 02, February 1993, p. 397, suggests solder carriers the size of an SMT component for depositing solder on substrates. The solder is screened into cavities (blind holes) in the carrier, then the carrier is placed on a PC card.
In one embodiment the carrier consists of three parts including a screen plate with through holes aligned with holes in a carrier plate and a solid back plate. The screen plate is removed, the carrier plate is placed on the card, the back plate is removed, the component is placed on the carrier plate, and the solder paste is reflowed. In a second embodiment using the same three parts, the back plate is removed, the carrier plate is placed on the card, the solder is reflowed, the screening plate is removed, a component is placed on the carrier plate and the solder is reflowed again. In a third embodiment using the same three parts, the solder is reflowed then the back plate is removed, the carrier plate is placed on the card, the solder is reflowed again, the screen plate is removed, a component is placed on the carrier plate and the solder is reflowed for the third time.
In a final embodiment the carrier is one plate with cavities filled with solder paste, which is placed cavity down on the PC card and the solder paste is reflowed to deposite the solder onto the card, then the plate is mechanically removed or dissolved by solvent. Then the component is placed on the site and the solder is reflowed.
U.S. Pat. No. 5,196,726 to Nishiguchi suggests packaging substrates with recesses containing plated electrode terminals (100 .mu.m dia) covered by a vacuum deposited solder with a lower melting temperature than the bumps (e.g. Au/20% Sn or Pb/40% Sn). Bumps of an IC chip (80 .mu.m dia and 30 .mu.m high) fit the recesses.
U.S. Pat. No. 5,024,372 to Altman suggests forming solder bumps by applying at least a 10 mil preferably 15 mil, thick layer of photo definable solder resist to a ceramic, polyimide, or circuit-board substrate; selectively removing resist to form wells over metal pads in a grid array on the substrate; using a squeegee to apply solder paste into the wells; reflowing the paste; and removing the resist. It also suggests connecting a solder bumped member to a substrate by forming the wells filled with a solder paste (having a melting temperature lower than the solder bumps) over pads on the substrate in a pattern corresponding to the solder bumps; positioning the member over the substrate so that the bumps settle into the solder paste; and reflow heating to melt the solder paste but not the solder bumps to wet the metal pads and blend with the solder bumps.
U.S. Pat. No. 5,388,327 to Trabucco discloses injecting liquid solder into holes formed through a dissolvable film carrier onto contact pads of a ball grid array module to form solder balls. The film may be soluble in water, acitone, or in a flux solvent such as CFCs or turpenes.
JP 4-263433 A to Watanabe suggests recessions in a surface which are filled with a metallic paste by a sliding squeegee, and then heating to 230.degree. C. using a heating head to melt the paste and form metallic balls. Then electrode pads of an IC chip are pressure-fixed to the balls in the recessions to form electric connection contacts.
U.S. Pat. No. 4,311,267 to Lim suggests connecting leads (tins) to SIP or DIP packages by: forming interconnected conductive pads on a alumina ceramic substrate (0.5 by 1.0 inches), by thick film techniques and including lead pads (70 by 80 mils) and component pads (70 mils square); clipping leads (10 by 20 mil) to the substrate edge at lead pads; and screening solder paste through a stencil onto the leads, lead pads, and component pads. The citation suggests chemically milling brass stencils from both sides by: coating with photoresist; applying artwork negatives to both sides; exposing to light through the artwork; developing and washing away the unexposed resist; and etching from both sides. Then a 1 mil layer of nickel is plated onto the stencil plate to improve abrasion resistance by increasing surface hardness. The citation suggests several sources of screen printing machines for printing solder paste and describes their operation.
U.S. Pat. Nos. 5,211,764 and 5,346,118 to Degani suggests printing Sn/Pb/Bi 43/43/14 solder through a 21 mil (up to 30 mil) thick stencil with rectangular openings which taper at an angle 5-10.degree. (less than 450) from vertical from a narrow top opening (60 mil) to a wider bottom opening (64 mil) onto a 10 by 10 grid array of about 33 mil pads on 100 mil centers (as low as 30 mil pads on 60 mil centers) to produce bumps (up to 30 mil high have been demonstrated) on an IC circuit on a wafer. The bottom opening area is up to 5 times larger than the pad area and double printing (i.e. print and reflow, then print and reflow again) can be used to increase paste volume. The paste includes a special flux and additives to provide low stickiness and metal loading is increased to as high as 80% by volume by using two different sized powers. Using paste with a high ratio of metal volume minimize slump so that (hole bottom diameter)/(stencil thickness) can be as low as 1.5, but preferably 2.5, and (hole bottom diameter)/(pad spacing) can be as low as 0.75.
U.S. Pat. No. 4,722,470 to Johary suggests forming an array of two rows of rectangular, non-reentrant cavities in a solid block or plate of titanium (a material non-wetted by solder), in a pattern matching a pattern of J-leads on a PLCC; loading the cavities with solder paste by wiping solder paste on the plate surface with blade or squeegee to force the paste into the cavities; coating all but the end portion of the J-lead with solder resist; aligning the J-leads in registration with the cavities with an exposed portion of each J-lead in contact with the paste; and reflowing the paste to form a mass of molten solder on the end portion of each J-lead. Johary suggests "Lead to lead spacing of 0.050 inch are common, and closer spacing such as 0.025 inch are anticipated"; also "Surface mount techniques are used to secure a wide variety of components or devices" and "the invention is applicable as well to other lead configuration such as outwardly extending gull-wing leads, downwardly extending I leads and other leads or metallizations of various types."
The entire disclosure of the above citations is hereby incorporated by reference.